The present invention generally relates to differential receivers, and more particularly to high speed CMOS differential receivers.
FIG. 1 illustrates an example of a data signal 10 represented by differential signals 12 and 14, which are opposite of one another. When data signal 10 transitions from a logic low 11 to a logic high 13 differential signal 12 transitions from a high value 15 to a low value 16 and differential signal 14 transitions from a low value 17 to a high value 18, each signal remaining opposite of the other. This transition represents a change in data, which can be converted to a single output signal.
Typically, a wide band differential receiver is used to meet the sensitivity requirements of today""s high data rate technology. The receiver amplifies the input signal to the target signal level. Also, the data pulse width distortion needs to be minimized so that the integrity of the bitstream is maintained during amplification.
FIG. 2 illustrates an example of a differential receiver currently used in high speed data transmission. The differential receiver of FIG. 2 contains two P-channel metal-oxide semiconductor (xe2x80x9cPMOSxe2x80x9d) transistors 20 and 22, and four N-channel metal-oxide semiconductor transistors (xe2x80x9cNMOSxe2x80x9d) 24, 26, 28, and 29. Input signals +VIN 14 and xe2x88x92VIN 12 are received on the gates of NMOS transistors 28 and 29, respectively. When input signals 12 and 14 transition from low to high or from high to low the output signals +VOUT 200 and xe2x88x92VOUT 201 must also transition from low to high or high to low. This output signal transition is a xe2x80x9crail-to-railxe2x80x9d transition, i.e., the output signals transitions from VDD to ground or ground to VDD.
One of the drawbacks of existing differential receivers, such as the one described with respect to FIG. 2, is the resulting distortion which occurs due to the rail-to-rail transition. This distortion results from a transition delay which occurs when transistors P20 or P22 operate in the triode region. Inherent in FIG. 2 is that the transition from a high signal to a low signal will be faster than transition from a low signal to a high signal because N28 and N29 are designed with a higher drive strength. This distortion in transition time results in a narrower pulse width when converted to a single logic signal, thereby distorting the data.
Additionally, other distortions may be introduced into the output signal as a result of internal circuit variations, such as process, temperature, power supplies and loading of additional circuits which may be coupled to the receiver.
Thus, a wide band differential receiver which reduces distortion and transition time, and which is not process or load dependent would represent an advancement in the art.
Roughly described, an aspect of the present invention comprises a differential receiver circuit that includes a first signal input node, a second signal input node, a plurality of transistors coupled with the first signal input node and the second signal input node, and a signal conditioning device coupled with the plurality of transistors.
According to another aspect, a differential receiver circuit that includes a current source and a plurality of transistors is provided. Included in the plurality of transistors is a first transistor of a first conductivity type having a source region coupled to the current source, a drain region, and a gate, and a second transistor of the first conductivity type having a source region coupled to another current source, a drain region, and a gate coupled to the gate of the first transistor. Also included in the plurality of transistors is a third transistor of a second conductivity type having a drain region coupled to the drain region of the first transistor, a source region, and a gate, and a fourth transistor of the second conductivity type having a drain region coupled to the drain region of the second transistor, a source region, and a gate coupled to the gate of the third transistor. A first signal conditioning device having an input node coupled to the drain of the third transistor and the drain of the first transistor and an output node coupled to the drain of the fourth transistor and the drain of the second transistor is also included in the differential receiver. Additionally, a second signal conditioning device having an input node coupled to the drain of the fourth transistor and the drain of the second transistor and an output node coupled to the drain of the third transistor and the drain of the first transistor is described.